1 data sheet acquired from harris semiconductor schs118 features ? buffered inputs ? typical propagation delay: 7ns at v cc = 5v, c l = 15pf, t a = 25 o c ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) ? cmos input compatibility, i l 1 m a at v ol , v oh description the harris cd54hc08, cd54hct08, cd74hc08 and cd74hct08 logic gates utilize silicon gate cmos technology to achieve operating speeds similar to lsttl gates with the low power consumption of standard cmos integrated circuits. all devices have the ability to drive 10 lsttl loads. the 74hct logic family is functionally pin compatible with the standard 74ls logic family. pinout cd54hc08, cd54hct08, cd74hc08, cd74hct08 (pdip, cerdip, soic) top view ordering information part number temp. range ( o c) package pkg. no. cd74hc08e -55 to 125 14 ld pdip e14.3 cd74hct08e -55 to 125 14 ld pdip e14.3 cd74hc08m -55 to 125 14 ld soic m14.15 cd74hct08m -55 to 125 14 ld soic m14.15 cd54hc08f -55 to 125 14 ld cerdip f14.3 cd54hct08f -55 to 125 14 ld cerdip f14.3 cd54hc08w -55 to 125 wafer cd54hct08w -55 to 125 wafer cd54hc08h -55 to 125 die cd54hct80h -55 to 125 die note: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 1a 1b 1y 2a 2b 2y gnd v cc 4b 4a 4y 3b 3a 3y 1 2 3 4 5 6 7 14 13 12 11 10 9 8 august 1997 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1997 file number 1549.1 cd54hc08, cd54hct08, cd74hc08, cd74hct08 high speed cmos logic [ /title (cd54h c08, cd54h ct08, cd74h c08, cd74h ct08) / sub- j ect (high
2 functional diagram hc logic symbol hct logic symbol truth table inputs output na nb ny lll lhl hll hhh note: h = high voltage level, l = low voltage level 1a 1b 2a 2b 2y gnd 1 2 3 4 5 6 14 13 12 11 v cc 4y 3y 3b 4a 4b 10 8 7 9 3a 1y na nb ny na nb ny cd54hc08, cd54hct08, cd74hc08, cd74hct08
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 2) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 100 n/a cerdip package . . . . . . . . . . . . . . . . 130 55 soic package . . . . . . . . . . . . . . . . . . . 180 n/a maximum junction temperature (hermetic package or die) . . . 175 o c maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 2. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads ---------v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads ---------v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a cd54hc08, cd54hct08, cd74hc08, cd74hct08
4 quiescent device current i cc v cc or gnd 0 6 - - 2 - 20 - 40 m a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 2 - 20 - 40 m a additional quiescent device current per input pin: 1 unit load (note) d i cc v cc - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: for dual-supply systems theorectical worst case (v i = 2.4v, v cc = 5.5v) speci?cation is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads all 0.6 note: unit load is d i cc limit speci?ed in dc electrical speci?cations table, e.g. 360 m a max at 25 o c. switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units min typ max min max min max hc types propagation delay, input to output (figure 1) t plh , t phl c l = 50pf 2 - - 90 - 115 - 135 ns 4.5 - - 18 - 23 - 27 ns 6 - - 15 - 20 - 23 ns propagation delay, data input to output y t plh , t phl c l = 15pf 5 - 7 - ----ns cd54hc08, cd54hct08, cd74hc08, cd74hct08
5 transition times (figure 1) t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns input capacitance c i - - - - 10 - 10 - 10 pf power dissipation capacitance (note 3, 4) c pd - 5-37-----pf hct types propagation delay, input to output y (figure 2) t plh , t phl c l = 50pf 4.5 - - 25 - 31 - 38 ns propagation delay, data input to output y t plh , t phl c l = 15pf 5 - 10 - ----ns transition times (figure 2) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i c l = 50pf - - - 10 - 10 - 10 pf power dissipation capacitance (notes 3, 4) c pd - 5-51-----pf notes: 3. c pd is used to determine the dynamic power consumption, per gate. 4. p d = v cc 2 f i (c pd + c l ) where f i = input frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units min typ max min max min max test circuits and waveforms figure 3. hc and hcu transition times and propaga- tion delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% cd54hc08, cd54hct08, cd74hc08, cd74hct08
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